Integrated circuits (IC) manufactures are constantly striving to reduce semiconductor device sizes. It has been the trend in integrated circuit (IC) technology to make small, high speed and high-density devices. Thus, the density of semiconductor devices per unit area of silicon wafer is increased. However, the high density integration of circuits makes the process more difficult, and also makes the testing methods more difficult for ensuring and promoting the qualities of the devices which are produced. For example, various testing methods are required for the chips between performing the step of dividing wafers to chips and packaging the chips completely. Wherein some testing methods are used to ensure the completed package devices conforming to functional and life-time requirements. Besides, low cost and much time efficiency for performing the various testing methods are important concerned issues.
In general, all tests performed before the chips divided from the wafers are called wafer level tests, such as CP1, CP2, WAT and so on. The WAT tests are used for sampling wafers under inspecting control in wafer process. The WAT tests, such as dielectric test, low voltage field effect transistor and high voltage field effect transistor tests (LVFET & HVFET testing), P-N junction test, OPEN/SHOT test and so on, are used for real-time controlling the qualities of wafers in processes. The CP1 tests comprise of the OPEN/SHOT test and some gross tests, and the CP2 tests comprise of the full function test for the chips on wafers. It is noted that the laser-repairing processes are used to promote the qualities and yields of some chips that can be amended, such as chips for memory, before performing the CP2 tests. In addition, the tests described above within a temperature range about from -5.degree. C./90 .degree. C. to 105.degree. C. are used for eliminating some chips which will cause breakdown easily in order to ensure the chips retained all have good qualities, and can maintain a longer life-time.
The tests for testing the chips, such as memory chips, in the period between dividing the chips from the wafers and completing the packages of chips are called chip level tests. Wherein the chip level tests comprising of FT1, FT2, FT3 and so on tests, are used for performing some tests which can't be done in wafer level tests, and for providing testing conditions much temperature differences for testing the chips, in order to eliminate some chips with defects and ensure the qualities and operating life-time of package devices satisfying the requirements. There is a burn-in process for accelerated maturing the chips between performing FT1 tests (namely the open shot & gross tests) and FT2 tests (namely full function test). The burn-in process is used for rapidly eliminating some devices which will breakdown prematurely, in order to ensure the packaged devices maintaining a longer life-time required. Briefly, there is a series of precondition and testing process used to promote the reliable capacities of the package devices. The relations between the developments of packaging models and testing methods are closely. Any packaging model that cannot be used for performing tests and costs much will be eliminated unless with some special functions that others cannot perform.
However, for the chips just packed to the substrate using the flip chip bumps but packaging, it's difficult to perform FT1, FT2, and FT3 tests except the wafer level tests, such as CP1, CP2, WAT and so on. The main factor of above issues is that it is difficult to hold the fine chips and execute the sequential testing processes by using current apparatus and testing methods. It is required to develop the new testing apparatus for solving the issues above. Especially, the developments of the trays used to hold the chips, the drawer used for drawing the chips, automatic loading & unloading system, the test socket and so on, will cost much since there is not any unified standards.
Besides, the tolerance of conducting points located on chips for tests is generally below 20 .mu.m. Relatively, the tolerance of the testing apparatus produced according to the prior technique is more than 25 .mu.m. The tolerances caused the more incorrect judgements easily. Currently, the precisely alignment between the outer leads of the testing devices and the conducting points of the test sockets are obtained by deciding the exterior sizes and the allowed tolerance of the testing devices. However, the testing methods can't apply to test the chips without packages unless the pitches of testing points and the conducting area can overcome the tolerance caused by alignments between the testing devices and test sockets. Another solution is using a vision system added on the testing apparatus to make the alignment more precisely. In conclusion, it's essential to manufacture test sockets by using the techniques of producing chips and to test the chips by using a vision system for alignments whether the redistribution of the testing points of chips is performed, in order to avoid incorrect judgements and complete testing chips with any size. A novel method according to present invention is proposed to perform the tests for chips with flip chip bumps by using the current test apparatuses. The tests performed comprise of the FT1, FT2, and BURN-IN tests. The qualities and operating life-time for the chips located on the substrate are under control by using the method proposed according the present invention.